H-S Philip Wong - Curriculum Vitae

H.-S. Philip WONG Professor of Electrical EngineeringDepartment of Electrical Engineering and Center for Integrated Systems Stanford University 1982    Bachelor of Science, University of Hong Kong 1983    Master of Science, State University of New York at Stony Brook 1988    Ph.D., Lehigh University Prof. Wong joined Stanford in September, 2004 after 16 years at IBM Research, T.J. Watson Research Center, Yorktown Heights, New York. While at IBM, he worked on CCD and CMOS image sensors, double-gate/multi-gate MOSFET, device simulations for advanced/novel MOSFET, strained silicon, wafer bonding, ultra-thin body SOI, extremely short gate FET, germanium MOSFET, carbon nanotube FET, and phase change memory. He held various positions from Research Staff Member to Manager, and Senior Manager. While he was Senior Manager, he had the responsibility of shaping and executing IBM's strategy on nanoscale science and technology as well as exploratory silicon devices and semiconductor technology. His research interests are in nanoscale science and technology, semiconductor technology, solid state devices, and electronic imaging. He is interested in exploring new materials, novel fabrication techniques, and novel device concepts for future nanoelectronic systems. Novel devices often enable new concepts in circuit and system designs. His research also includes explorations into circuits and systems that are device-driven. His present research covers a broad range of topics including carbon nanotubes, semiconductor nanowires, self-assembly, exploratory logic devices, nanoelectromechanical devices, novel memory devices, and biosensors. He is a Fellow of the IEEE and served on the IEEE Electron Devices Society (EDS) as elected AdCom member from 2001 - 2006. He served on the IEDM committee from 1998 to 2007 and was the Technical Program Chair in 2006 and General Chair in 2007. He served on the ISSCC program committee from 1998 - 2004, and was the Chair of the Image Sensors, Displays, and MEMS subcommittee from 2003-2004. Currently, he serves on the Executive Committee of the Symposia of VLSI Technology and Circuits. He was the Editor-in-Chief of the IEEE Transactions on Nanotechnology in 2005 - 2006. He is a Distinguished Lecturer of the IEEE Electron Devices Society (since 1999) and Solid-State Circuit Society (2005 - 2007). He has taught several short courses at the EDM, ISSCC, Symp. VLSI Technology, SOI conference, and SPIE conferences. He is a member of the Emerging Research Devices Working Group of the International Technology Roadmap fo Semiconductors (ITRS).